Personally I don’t assume we'll see the line between memory and storage be all that muddled in the future. Yes, Memory Wave 3D XPoint is a lot more responsive than Flash. However Flash isn’t all that impressive as is. The standard exhausting drive has entry latencies around 4ms on common. Flash can reach well bellow µs latency, but for very small arrays. That is expensive and largely seen in Microcontrollers that execute straight from their Flash. "Enterprise grade" flash that optimizes at price/GB will have far greater latency, in the few to tens of µs area. 3D Xpoint is a little bit of a wash. I have seen quoted figures of sub 350ns write latency, however that is probably going for a single cell, not an array. Optane modules from Intel alternatively have typical latencies around 5-15µs, but that is from a "system" perspective, ie, protocol and controller overhead comes into play, Memory Wave System as well as one’s software environment.
DRAM however has entry latencies round 2-15ns at present. The issue with latency is that it leads to our processor stalling on account of not getting the info in time. One can prefetch, however branches makes prefetching tougher, since what aspect should you fetch? Department prediction partly solves this concern. But from a performance standpoint, we must always fetch both sides. But when we now have extra latency, we have to prefetch even earlier, risking extra branches. In other phrases, peak bandwidth required by our processor increases at an exponential charge in comparison with latency. A fee that is application dependent as properly. Caching might sound like the trivial solution to the issue, but the effectivity of cache is proportional to the latency. To a degree, cache is a magic bullet that just makes Memory Wave System latency disappear. However each time an application calls for one thing that isn’t in cache, then the application stalls, as long as there may be threads to take its place that also have data to work on, then you definately won’t have a performance deficit apart from thread switching penelties, however for those who don’t have such threads, then the CPU stalls.
One can make sure that more threads have their data by just making the cache larger, but cache is so much costlier than DRAM. In the end, all of it results in the fact that growing latency will require an arbitrary amount more cache for a similar system performance. Going from the few ns latency of DRAM to the couple of µs latency of current persistent memory is just not practical as an actual alternative for DRAM, even if it reduces its latency to a one centesimal it is still not impressive so far as memory goes. Although, the use of persistent DIMMs for storage caching or as a "RAM drive" of sorts nonetheless has main advantages, however for program execution it's laughable. And i don’t suspect this to vary any time soon. But I can see a future the place the principle memory relocates into the CPU. Where the CPU itself has an HBM memory chip or four on it supplying comparatively low latency and high bandwidth memory to the CPU, while the external buses are used for IO and storage. However this isn’t all that reasonable in more skilled purposes, since some workstation functions honestly needs 10’s-100’s of GB of precise RAM to get good performance.
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